Statistical static timing analysis
Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis,, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
Why STA is popular
Old fashioned deterministic STA is popular for good reasons:
- It requires no vectors, so it does not miss paths
- Run time is linear in circuit size
- The result is conservative
- Can use some fairly simple libraries (typically delay and output slope as a function of input slope and output load).
- Easy to extend to incremental operation for use in optimization