SHA instruction set
Intel SHA Extensions are a set of extensions to the x86 instruction set architecture which support hardware acceleration of Secure Hash Algorithm (SHA) family. It was specified in 2013.[1] Instructions for SHA-512 will be introduced in Arrow Lake and Lunar Lake in 2024.
The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256.
- SHA-1:
SHA1RNDS4,SHA1NEXTE,SHA1MSG1,SHA1MSG2 - SHA-256:
SHA256RNDS2,SHA256MSG1,SHA256MSG2
The newer SHA-512 instruction set comprises AVX-based versions of the original SHA instruction set marked with a V prefix and these three new AVX-based instructions for SHA-512:
VSHA512RNDS2,VSHA512MSG1,VSHA512MSG2
x86 architecture processors
AMD
All recent AMD processors support the original SHA instruction set:
Intel
The following Intel processors support the original SHA instruction set:
- Intel Goldmont[3] (2016) and later Atom microarchitecture processors.
- Intel Cannon Lake[4] (2018/2019), Ice Lake[5] (2019) and later processors for laptops ("mainstream mobile").
- Intel Rocket Lake (2021) and later processors for desktop computers.
The following Intel processors will support the newer SHA-512 instruction set:
- Intel Arrow Lake and Lunar Lake processors.
References
- ^ "New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors". intel.com. Retrieved 2024-07-25.
- ^ "Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
- ^ "Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
- ^ "Cannon Lake - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
- ^ "Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2024-07-25.
External links
- Chapter 8 of "Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Archived from the original (PDF) on 2013-09-29.
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