Complex instruction set computer

A complex instruction set computer (CISC) is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. The term was retroactively coined in contrast to reduced instruction set computer (RISC).

Before the first RISC processors were designed, many computer architects tried to bridge the "semantic gap" - to design instruction sets to support high-level programming languages by providing "high-level" instructions such as procedure call and return, loop instructions such as "decrement and branch if non-zero" and complex addressing modes to allow data structure and array accesses to be combined into single instructions. The compact nature of such a CISC ISA results in smaller program sizes and fewer calls to main memory, which at the time (the 1960s) resulted in a tremendous savings on the cost of a computer.

While many designs achieved the aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions, it was observed that this was not always the case. For instance, badly designed, or low-end versions of complex architectures (which used microcode to implement many hardware functions) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call instruction), but instead using a sequence of simpler instructions.

One reason for this was that such high level instruction sets, often also highly encoded (for a compact executable code), may be quite complicated to decode and execute efficiently within a limited transistor budget. These architectures therefore requires a great deal of work on the part of the processor designer (or a slower microcode solution). At the time where transistors were a limited resorce, this also left less room on the processor to optimize performance in other ways, which gave room for the ideas that lead to the original RISC designs in the mid 1970 (IBM 801 - IBMs Watson Research Center).

Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, and AMD and Intel x86 CPUs.

The terms RISC and CISC has become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly pipelined "CISC" implementations, such as 486s from Intel, AMD, Cyrix, and IBM, certainly supported every instruction that their predecessors did, but achieved high efficiency only on a fairly simple x86 subset (resembling a RISC instruction set, but without the load-store limitations of RISC). Modern x86 processors also decode and split more complex instructions into a series of smaller internal "micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions.

See also