Multi-threshold CMOS

Multi-CMOS (MTCMOS) utilized transistors with multiple threshold voltages (Vt) to optimize delay or power. Lower Vt devices are used on critical delay paths to minimize clock periods. Higher Vt devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. One method of creating devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or bulk terminal of transistors. In NMOS devices, lower Vb will increase Vt, increase delay, and reduce static leakage.--Grgkchen 02:27, 29 January 2007 (UTC)