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Fair computational tree logic

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Fair Computational tree logic is conventional Computational tree logic studied with explicit fairness constraints.

References

References

  • Emerson, E. A. and Halpern, J. Y. (1985). "Decision procedures and expressiveness in the temporal logic of branching time". Journal of Computer and System Sciences. 30 (1): 1–24.{{cite journal}}: CS1 maint: multiple names: authors list (link)
  • Clarke, E. M., Emerson, E. A., and Sistla, A. P. (1986). "Automatic verification of finite-state concurrent systems using temporal logic specifications". ACM Transactions on Programming Languages and Systems. 8 (2): 244–263.{{cite journal}}: CS1 maint: multiple names: authors list (link)
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