Permute instruction

Permute instructions copy unaltered contents from a source array to a destination array, where the indices are specified by a second source array. The size (bitwidth) of the source elements is not restricted but remains the same as the destination size.

There exists two important variants, known as gather and scatter, respectively. The scatter variant is as follows:

for i = 0 to length-1
   dest[i] = src[indices[i]]

where the gather variant is:

for i = 0 to length-1
   dest[indices[[i]] = src[i]

The scatter variant can be seen to "scatter" the source elements across (into) to the destination, where the "gather" variant is gathering data from the source elements.

Given that the indices may be repeated in both variants, the resultant output is not a strict mathematical permutation because duplicates can occur in the output. Permute instructions, misleadingly, actually create combinations.

A special case of permute is also used in GPU "swizzling" (again, actually a combination) which performs on-the-fly reordering of subvector data so as to align or duplicate elements with the appropriate SIMD lane.

Occurrences of permute instructions

Permute instructions can occur in both scalar processors as well as Vector processing engines as well as [[GPU]s. In Vector instruction sets they are typically named "Register Gather/Scatter" operations, and take Vectors as input for both source elements and source array, and output another Vector.

In scalar instruction sets the scalar registers are broken down into smaller sections (unpacked, SIMD style) where the fragments are then used as array sources. The (small, partial) results are then concatenated (packed) back into the scalar register as the result.

Some ISAs, particularly for cryptographic applications, even have bit-level permute operations, such as in RISC-V bitmanip. Also in some non-Vector ISAs, due to there sometimes being insufficient space in the one source input register to specify the permutation source array in full (particularly if the operation involves bit-level permutation), will include partial reordering instructions. Examples include VSHUFF32x4 from AVX-512#Permute and bdep (bit deposit) from RISC-V bitmanip.

Permute operations in different forms are surprisingly common, occurring in AltiVec, Power ISA, PowerPC G4, AVX-512 and in Vector processors as well as GPUs