Advanced Vector Extensions

Advanced Vector Extensions (AVX) is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.

AVX provides new features, new instructions and a new coding scheme.

New features

The width of the SIMD register file is increased from 128 bits to 256 bits, and renamed from XMM0–XMM15 to YMM0–YMM15. In processors with AVX support, the legacy SSE instructions (which previously operated on 128-bit XMM registers) now operate on the lower 128 bits of the YMM registers. Further extensions to 512 or 1024 bits are expected in the future.Vorlage:Citation needed

AVX introduces a three-operand SIMD instruction format, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form a = a + b can now use a non-destructive three-operand form c = a + b, preserving both source operands. AVX's three-operand format is limited to the instructions with SIMD operands (YMM), and does not include instructions with general purpose registers (e.g. EAX), but such support may be added in the future.Vorlage:Citation needed

The alignment requirement of SIMD memory operands is relaxed.

New coding scheme

The new VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits.

New instructions

Instruction	Description
VBROADCASTSS, VBROADCASTSD, VBROADCASTF128	Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.
VINSERTF128	Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
VEXTRACTF128	Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
VMASKMOVPS, VMASKMOVPD	Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.
VPERMILPS, VPERMILPD	Shuffle 32-bit or 64-bit vector elements, with a register or memory operand as selector.
VPERM2F128	Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
VZEROALL	Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.
VZEROUPPER	Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.

Applications

• Suitable for floating point-intensive calculations in multimedia, scientific and financial applications (integer operations are expected in later extensions).
• Increases parallelism and throughput in floating point SIMD calculations.
• Reduces register load due to the non-destructive instructions.

Compiler and assembler support

Recent releases of GCC starting with 4.6 (although there was a 4.3 branch with certain support) and the Intel Compiler Suite support AVX starting with version 11.1. The Visual Studio 2010 compiler supports AVX via intrinsic and /arch:AVX switch. The GNU Assembler (GAS) inline assembly functions support these instructions (accessible via GCC), as do Intel primitives and Intel inline assembler (closely compatible to GAS, although more general in its handling of local references within inline code). Other assemblers such as MASM VS2010 version, YASM 1.1.0, FASM and NASM also apparently support AVX instructions.

Operating system support

AVX adds new register-state through the 256-bit wide YMM register file, so explicit operating system support is required to properly save & restore AVX's new registers between context switches. The following operating system versions will support AVX:

• Apple OS X: Support for AVX added in 10.6.8 (Snow Leopard) update released on June 23, 2011.
• Linux: supported since kernel version 2.6.30, released on June 9, 2009.
• Windows: supported in Windows 7 SP1 and Windows Server 2008 R2 SP1.; hotfix 2517374 available for non-SP1 version of Windows Server 2008 R2.; Windows 8

CPUs with AVX

• Intel
  • Sandy Bridge processor, Q1 2011.
  • Ivy Bridge processor, Q1 2012.

• AMD:
  • Future Bulldozer processor, Q3 2011.

Issues regarding compatibility between future Intel and AMD processors are discussed under XOP instruction set.

Future instruction sets

The VEX coding scheme allows future extensions of the SIMD register size.

Descriptions of other future x86 instruction sets:

• Intel FMA3
• AMD FMA4
• AMD XOP
• AMD CVT16

Advanced Vector Extensions 2

Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions, is an expansion of the AVX instruction set to be first introduced in Intel's Haswell microarchitecture. AVX2 makes the following additions:

• Expansion of integer SIMD types to 256 bits
• General-purpose bit manipulation instructions
• Gather support, enabling vector elements to be loaded from non-contiguous memory locations
• DWORD- and QWORD-granularity any-to-any permutes
• Vector shifts
• Fused multiply-accumulate support

CPUs with AVX2

• Intel
  • Haswell processor, 2013.
  • Broadwell processor, 2014.