Soft microprocessor
Un processador softcore és un processador (CPU) implementat en un sistema reprogramable com una FPGA. Això es coneix com un sistema en un xip programable (System on a Programmable Chip o SOPC).
Comparació de nuclis
| Processor | Developer | Open Source | Bus Support | Notes | Project Home | Description Language |
|---|---|---|---|---|---|---|
| TSK3000A | Altium | no Royalty-Free | Wishbone | 32-bit R3000 style RISC Modified Harvard Architecture CPU | Embedded Design on Altium Wiki | |
| TSK51/52 | Altium | (noruec) Royalty-Free | Wishbone / Intel 8051 | 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative | Embedded Design on Altium Wiki | |
| OpenSPARC T1 | Sun | si | 64-bit | OpenSPARC.net | Verilog | |
| MicroBlaze | Xilinx | no | PLB, OPB, FSL, LMB, AXI4 | Xilinx MicroBlaze | ||
| PicoBlaze | Xilinx | si | Xilinx PicoBlaze | VHDL, Verilog | ||
| Nios, Nios II | Altera | no | Avalon | Altera Nios II | Verilog | |
| Cortex-M1 | ARM | no | [1] | 70-200 MHz, 32bit RISC | [2] | Verilog |
| eSi-RISC | EnSilica | no | AMBA AXI, AHB and APB | Configurable as 16 or 32-bit. Supports ASIC and FPGA. | EnSilica eSi-RISC | Verilog |
| LatticeMico32 | Lattice | si | Wishbone | LatticeMico32 | Verilog | |
| LEON2(-FT) | ESA | si | AMBA2 | SPARC V8 | ESA | VHDL |
| LEON3/4 | Aeroflex Gaisler | si | AMBA2 | SPARC V8 | Aeroflex Gaisler | VHDL |
| Navré | Sébastien Bourdeauducq | si | Direct SRAM | Atmel AVR compatible 8-bit RISC | Project page at Opencores | Verilog |
| OpenRISC | OpenCores | si | Wishbone | 32-bit; Done in ASIC, Actel, Altera, Xilinx FPGA | OR1K | Verilog |
| ARC | ARC International, Synopsys | no | 16/32-bit ISA RISC | DesignWare ARC | Verilog | |
| pAVR | Doru Cuturela | si | Atmel AVR compatible 8-bit RISC | Project page at Opencores | VHDL | |
| AEMB | Shawn Tan | si | Wishbone | MicroBlaze EDK 3.2 compatible | AEMB | Verilog |
| OpenFire | Virginia Tech CCM Lab | si | OPB, FSL | Binary compatible with the MicroBlaze | [3] [1] | Verilog |
| SecretBlaze | LIRMM, University of Montpellier / CNRS | si | Wishbone | MicroBlaze ISA, VHDL | SecretBlaze | VHDL |
| RISC-V | UC Berkeley | si | RISC-V ISA, Xilinx Zynq | riscv.org | Chisel | |
| SYNPIC12 | Miguel Angel Ajo Pelayo | si MIT | PIC12F compatible, program synthesised in gates | nbee.es | VHDL | |
| PacoBlaze | Pablo Bleyer | si | Compatible with the PicoBlaze processors | PacoBlaze | Verilog | |
| CPU86 | HT-Lab | si | 8088 compatible CPU in VHDL | cpu86 | VHDL | |
| xr16 | Jan Gray | no | XSOC abstract bus | 16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118 | XSOC/xr16 | Schematic |
| JOP | Martin Schoeberl | si | SimpCon / Wishbone (extension) | Stack oriented, hard real-time support, executes Java bytecode directly | Jop | VHDL |
| ERIC5 | Entner Electronics | no | 9-bit RISC, very small size, C-programmable | ERIC5 | VHDL | |
| YASEP | Yann Guidon | si AGPLv3 | Direct SRAM | 16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready | yasep.org (Firefox required) | VHDL |
| Zet | Zeus Gómez Marmolejo | si | Wishbone | x86 PC clone | Zet | Verilog |
| ZPU | Zylin AS | si | Wishbone | Stack based CPU, configurable 16/32 bit datapath, eCos support | Zylin CPU | VHDL |
| ZPUino | Álvaro Lopes | si | Wishbone | Zylin's ZPU based SoC, 32 bit, Linux support. | ZPUino | VHDL |