Information for "Simple Bus Architecture"
Basic information
| Display title | Simple Bus Architecture |
| Default sort key | Simple Bus Architecture |
| Page length (in bytes) | 6,834 |
| Namespace ID | 0 |
| Page ID | 41544036 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | Fewer than 30 watchers |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Wikidata item ID | Q16532775 |
| Central description | architecture for the SoC implementation based in VHDL |
| Page image |  |
| Page views in the past 30 days |
Page protection
| Edit | Allow all users (no expiry set) |
| Move | Allow all users (no expiry set) |
Edit history
| Page creator | Mrisco (talk | contribs) |
| Date of page creation | 03:51, 4 January 2014 |
| Latest editor | Kvng (talk | contribs) |
| Date of latest edit | 02:49, 26 December 2024 |
| Total number of edits | 56 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (15) | Pages transcluded onto the current version of this page (help):
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