| Display title | Multi-channel memory architecture |
| Default sort key | Multi-channel memory architecture |
| Page length (in bytes) | 23,632 |
| Namespace ID | 0 |
| Page ID | 2024036 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | 90 |
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| Number of redirects to this page | 20 |
| Counted as a content page | Yes |
| Wikidata item ID | Q1072927 |
| Local description | Computer memory architecture |
| Central description | computer memory architecture that increases bandwidth by attaching multiple memory channels to the DRAM controller |
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| Page creator | DoomBringer (talk | contribs) |
| Date of page creation | 07:09, 11 June 2005 |
| Latest editor | Juaner34 (talk | contribs) |
| Date of latest edit | 04:44, 12 November 2024 |
| Total number of edits | 550 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |
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