| Display title | Latency oriented processor architecture |
| Default sort key | Latency oriented processor architecture |
| Page length (in bytes) | 12,739 |
| Namespace ID | 0 |
| Page ID | 51623894 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | Fewer than 30 watchers |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Wikidata item ID | Q28455699 |
| Local description | Microarchitecture of a microprocessor designed to serve a serial computing thread with low latency |
| Central description | type of processor architecture |
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| Page creator | Mohitgupta2105 (talk | contribs) |
| Date of page creation | 12:07, 16 September 2016 |
| Latest editor | OAbot (talk | contribs) |
| Date of latest edit | 15:51, 29 January 2023 |
| Total number of edits | 35 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |
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