| Display title | Capability Hardware Enhanced RISC Instructions |
| Default sort key | Capability Hardware Enhanced RISC Instructions |
| Page length (in bytes) | 29,108 |
| Namespace ID | 0 |
| Page ID | 78845077 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | Fewer than 30 watchers |
| Number of redirects to this page | 3 |
| Counted as a content page | Yes |
| Wikidata item ID | Q131873099 |
| Local description | Computer architecture for security |
| Central description | computer architecture for security |
| Page views in the past 30 days | |
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| Move | Allow all users (no expiry set) |
| Page creator | BenLaurie (talk | contribs) |
| Date of page creation | 16:35, 9 January 2025 |
| Latest editor | 2a01:e0a:5a7:5010:81e0:e571:ceda:4b93 (talk) |
| Date of latest edit | 10:32, 22 July 2025 |
| Total number of edits | 120 |
| Recent number of edits (within past 30 days) | 5 |
| Recent number of distinct authors | 3 |
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