Prefetch buffer

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DDR SDRAM's prefetch buffer width is 2-bit.

The prefetch buffer is a memory cache located on modern RAM modules which stores data before it is actually needed. In addition to increased operation frequencies, decreased heat production, and increased latency, and increased bandwidth, the width of the prefetch buffer is increased with each successive standard of modern DDR SDRAM modules:

• DDR SDRAM's prefetch buffer width is 2-bit.
• DDR2 SDRAM's prefetch buffer width is 4-bit.
• DDR3 SDRAM's prefetch buffer width is 8-bit.

See also

• Random access memory

External links

• Prefetch buffer discussed in terms of Proxy-Side Pre-Pushing
• Effects of Limiting Prefetch-Buffer Interactions